1. Field of the Invention
The present invention relates to a summing circuit used in a digital system.
2. Description of the Related Art
In a digital signal processing system, an input digital signal is generally subjected to a filtering process using a convolution integration. The convolution integration is carried out through summation. Therefore, it is desired to execute a great deal of calculation in a higher speed and a higher precision. The summing circuit contributes to improvement in the processing speed and the calculation precision in the above-mentioned product and summation calculation, in addition to addition of a plurality of digital data.
FIG. 1 shows a typical summing circuit as a first conventional example. The first conventional example of the summing circuit is composed of a shifter 701, an adder 703 and a RAM 705. The shifter 701 shifts a k-bit input data into the LSB direction of the input data to output as a (mxe2x88x92n)-bit data. The adder 703 adds the (mxe2x88x92n) data and a previous summation data to output a new current m-bit summation data. The RAM 705 stores the summation data temporarily.
Referring to FIG. 1, a plurality of k-bit positive data are summed. While the summing result is stored in the RAM 705, the summation is carried out p times and an m-bit summation value is obtained. In this case, for the purpose of avoiding the cutting-off of a part of data without any overflow, it is necessary to satisfy the relation of m=k+n in (nxe2x88x921) less than log(p)xe2x89xa6n (the base of the logarithm is 2). In this case, the value m increases as the value n increases. As a result, the capacity of the RAM 705 necessary to store the summation also increases.
Next, FIG. 2 shows a summing circuit of the product and summation unit in Japanese Laid Open Patent Application (JP-A-Heisei 9-62653) as a second conventional example. Referring to FIG. 2, the second conventional example of the summing circuit is composed of a first adder 801, a second adder 803, a third adder 805, a register 809 and a multiplexer 807. The first adder 801 is provided for a calculation to a lower 8 bits of an output of the summing circuit. The second adder 803 is provided for a calculation to a middle 8 bits of the output of the summing circuit. The third adder 805 is provided for a calculation to an upper 8 bits of the output of the summing circuit. The register 809 stores the summing result temporarily. The multiplexer 807 outputs the calculating result of the summing circuit based on a signal supplied to a third input terminal 814.
The operation of the above summing circuit will be described. Referring to FIG. 2, a 8-bit data is supplied to a second input terminal 813 and is converted into a digit shift data 816 indicative of a digit shift quantity by a data converter 818. A barrel shifter 811 shifts a data signal from a first input terminal 812 in digit based on the digit shift data 816 to output a 16-bit data. Thus, a multiplying process is executed. Subsequently, the lower 8-bit data of the 16-bit data from the barrel shifter 811 is supplied to the first adder 801, and the upper 8-bit data is supplied to the second adder 803. Thus, the summing process is started.
The first adder 801 adds the lower 8-bit data from the barrel shifter 811 and a lower 8-bit data of a 24-bit data from the multiplexer 807 to output an addition result data to the register 809 as the lower 8-bit data of the summing circuit. Also, the first adder 801 outputs a lower carry signal to the register 809. In this case, the first adder 801 outputs the lower carry signal having the bit state of xe2x80x9c1xe2x80x9d to the register 809, when the overflow occurs in the data of the addition result.
The second adder 803 adds the upper 8-bit data of the 16-bit data from the barrel shifter 811 and a middle 8-bit data of the 24-bit data from the multiplexer 807 to output a summation resultant data to the register 809 as the middle 8-bit data of the summing circuit. In this case, the second adder 803 adds xe2x80x9c1xe2x80x9d to the least significant bit of the summation resultant data, when the lower carry signal is xe2x80x9c1xe2x80x9d. Also, the second adder 803 outputs the summation resultant data to the register 809 when the carry signal is xe2x80x9c0xe2x80x9d. Also, the second adder 803 outputs a middle carry signal to the register 809. Further, the second adder 803 outputs a middle carry signal of xe2x80x9c1xe2x80x9d when the overflow occurs in the summation resultant data.
The third adder 805 adds xe2x80x9c1xe2x80x9d to the least significant bit of an upper 8-bit data of the 24-bit data from the multiplexer 807 when the middle carry signal is xe2x80x9c1xe2x80x9d, and outputs the summation resultant data to the register 809. When the middle carry signal is xe2x80x9c0xe2x80x9d, the third adder 805 outputs the summation resultant data from the multiplexer 807 to the register 809 just as it is. One of the input terminals of the third adder 805 is grounded such that data of xe2x80x9c0xe2x80x9d is always inputted to the input terminal.
The register 809 holds the summation resultant data from the first adder 801, the lower carry signal, the summation resultant data from the second adder 803, the middle carry signal, and the summation resultant data from the third adder 805 by one period of a clock signal to output to the multiplexer 807.
The multiplexer 807 selectively outputs one of the data supplied through the third input terminal 814 and the data supplied from the register 809. That is, the multiplexer 807 outputs the input data of xe2x80x9c0xe2x80x9d supplied through the third input terminal 814 to another input terminal of the first adder 801, the carry input terminal of the second adder 803, another input terminal of the second adder 803, the carry input terminal of the third adder 805 and another input terminal of third adder 805 in response to the first clock signal. Also, the multiplexer 807 outputs the data supplied from the register 809 to the first, second and third adders in response to the second clock signal and the subsequent, as follows. That is, the multiplexer 807 outputs the summation resultant data supplied from the first adder 801 to the other input terminal of the first adder 801, the lower carry signal supplied from the first adder 801 to the carry input terminal of the second adder 803, the summation resultant data supplied from the second adder 803 to the other input terminal of the second adder 803, the middle carry signal supplied from the second adder 803 to the carry input terminal of the third adder 805, and the summation resultant data supplied from the third adder 805 to the other input terminal of the third adder 805.
The above summing circuit is a 24-bit adder composed of three 8-bit adders and one register. The lower carry signal from the first adder 801 and the middle carry signal from the second adder 803 are transmitted to the adders on the side of the upper bits at the time of the next clock, after being held in the register for one period time of the clock signal. In this way, the carry transmission time for the addition is made short so that it is possible to short the summing operation time.
In the first conventional example shown in FIG. 1, the relation of m less than k+n is attained when the capacity of the RAM, i.e., the data word length is constrained. In order to prevent an overflow, it is necessary to cut off a part of data before the adding operation. The lower bits of each input data are cut off in advance to produce (mxe2x88x92n)-bit data for the adding operation. In this method, when (k+nxe2x88x92m) becomes large, the summation precision is degraded largely.
On the other hand, in the second conventional example shown in FIG. 2, the data converter and the barrel shifter are used in the product and summation unit, to prevent an overflow in the summing circuit. However, this function is contained in the function for the multiplying process, and the summing circuit does not have the function as its internal function.
An object of the present invention is to provide a summing circuit in which degradation of the summation precision can be reduced without increasing a RAM capacity necessary to hold a summation resultant data.
In order to achieve an aspect of the present invention, a summing circuit includes a summing section and a shift bit searching section. The summing section receives an input data and a previous summation resultant data, bit-shifts the input data and the previous summation resultant data in response to first and second bit shift control signals, respectively. Also, the summing section adds the bit-shifted input data and the bit-shifted previous summation resultant data to generate a current summation resultant data and to output a part of the current summation resultant data as a shift bit calculation data. The shift bit searching section outputs the first and second bit shift control signals for addition of a next input data and the current summation resultant data to the summing section based on the shift bit calculation data.
The summing section includes a data holding section, a data shifter and a data adder. The data holding section holds the input data and the previous summation resultant data to output as first and second output data, respective. The data shifter shifts the first output data into a LSB (Least Significant Bit) direction in response to the first bit shift control signal to output a first shift data. Also, the data shifter shifts the second output data into the LSB direction in response to the second bit shift control signal to output a second shift data. The data adder adds the first and second shift data to output the current summation resultant data and the shift bit calculation data.
In this case, the data adder may include a first adder which adds the first and second shift data to output the current summation resultant data, and a memory unit which stores the current summation resultant data.
Also, the-data adder may includes a first adder which adds the first and second shift data to output the current summation resultant data.
The data holding section may include a first latch circuit which holds the input data to output the first output data, and a second latch circuit which holds the previous summation resultant data to output the second output data.
The data shifter may include a first shifter which bit-shifts the first output data based on the first bit shift control signal to output the first shift data, and a second shifter which bit-shifts the second output data based on the second bit shift control signal to output the second shift data.
The shift bit searching section may include a data searching section and a control data generating section. The data searching section outputs a third output data in response to a change of the shift bit calculation data. The control data generating section generates the first and second bit shift control signals based on the third output data.
In this case, the data searching section preferably includes a logical OR calculating circuit, and a flip-flop circuit which holds a logical OR output data outputted from the logical OR calculating circuit to output a third output data. At this time, the logical OR calculating circuit receives the shift bit calculation data and the third output data to output the logical OR output data. Instead, the data searching section may include a logical AND calculating circuit which calculates a logical AND of bits of the shift bit calculation data, a logical OR calculating circuit and a third latch circuit which holds a logical OR output data outputted from the logical OR calculating circuit to output a third output data. At this time, the logical OR calculating circuit receives the shift bit calculation data and the third output data to output the logical OR output data.
The control data generating section may include a fourth latch circuit, a second adder and a fifth latch circuit. The fourth latch circuit outputs the second bit shift control signal based on the third output data. The second adder adds the third output data and the first bit shift control signal to output a shift bit data. The fifth flip-flop generates the first bit shift control signal based on the shift bit data outputted from the second adder, the first bit shift control signal being outputted to the second adders
In order to achieve another aspect of the present invention, a method of summing a plurality of input data, includes:
bit-shifting an input data and a previous summation resultant data in response to first and second bit shift control signals, respectively;
adds the bit-shifted input data and the bit-shifted previous summation resultant data to generate a current summation resultant data, a part of the current summation resultant data being a shift bit calculation data; and
estimating the first and second bit shift control signals for addition of a next input data and the current summation resultant data based on the shift bit calculation data.